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power management 1 www.semtech.com sc1205 high speed synchronous power mosfet driver features applications revision: september 22, 2004 description the sc1205 is a cost effective dual mosfet driver de- signed for switching high and low side power mosfets. each driver is capable of driving a 3000pf load in 20ns max rise/fall time and has a 20ns max propagation de- lay from input transition to the gate of the power fet?s. an internal overlap protection circuit prevents shoot- through from vin to gnd in the main and synchronous mosfet?s. the adaptive overlap protection circuit en- sures the bottom fet does not turn on until the top fet source has reached a voltage low enough to prevent cross-conduction. the high current drive capability (3a peak) allows fast switching, thus reducing switching losses at high (up to 1mhz) frequencies without overheating the driver. the high voltage cmos process allows operation from 5-25 volts at top mosfet drain, thus making sc1205 suit- able for battery powered applications. connecting en- able pin (en) to logic low shuts down both drives and reduces operating current to less than 10ua. an under-voltage-lock-out circuit is included to guaran- tee that both driver outputs are low when the 5v logic level is less than or equal to 4.4v (typ) at supply ramp up (4.35v at supply ramp down). an internal temperature sensor shuts down all drives in the event of overtemperature. sc1205 is fabricated utilizing bi-cmos technology for low quiescent current. the sc1205 is of- fered in a standard so-8 package. ? fast rise and fall times (15ns typical with 3000pf load) ? 3 amp peak drive current ? 14ns max propagation delay (bg going low) ? adaptive non-overlapping gate drives provide shoot-through protection ? floating top drive switches up to 25v ? under-voltage lock-out ? overtemperature protection ? less than 10 a supply current when en is low ? low cost ? high density sunchronous power supplies ? motor drives/class-d amps/half bridge drivers ? high frequency (to 1.2 mhz) operation allows use of small inductors and low cost caps in place of electrolytics ? high efficiency portable computers ? battery powered applications typical application circuit vcore, 1.7v,40a +5v vin 5-12v rf rref ri 10nf 2.5m 10 sc2422a 12 9 2 3 1 13 7 5 6 11 14 4 10 15 16 8 out2 gnd vid3 vid2 vid4 out1 fb vid0 er rout oc- oc+ vid1 uvlo bgout vcc rref 70n03 sc1205 co bst tg dr n vs en bg gnd sc1205 co bst tg dr n vs en bg gnd 10u,cer 2200uf 70n03 70n03 70n03 to processor vid control
2 ? 2004 semtech corp. www.semtech.com power management sc1205 electrical characteristics absolute maximum ratings r e t e m a r a pl o b m y ss n o i t i d n o cm u m i x a ms t i n u v c c e g a t l o v y l p p u sv w s x a m i 7v d n g p o t t s bx a m v d n g p - t s b 0 3v n r d o t t s bx a m v n r d - t s b 7v d n g p o t n r dx a m v n g p - n r d 5 2 o t 2 -v e s l u p d n g p o t n r dx a m v e s l u p t e s l u p s n 0 0 1 <5 2 o t 5 -v d n g p o t s _ p v ox a m v d n g p - s p v o 0 1v n i p t u p n io c3 . 7 o t 3 . 0 -v n o i t a p i s s i d r e w o p s u o u n i t n o cd pt , c 5 2 = b m a t j c 5 2 1 = t , c 5 2 = e s a c t j c 5 2 1 = 6 6 . 0 6 5 . 2 w e s a c o t n o i t c n u j e c n a t s i s e r l a m r e h t c j 0 4w / c t n e i b m a o t n o i t c n u j e c n a t s i s e r l a m r e h t a j 0 5 1w / c e g n a r e r u t a r e p m e t g n i t a r e p ot j 5 2 1 + o t 0c e g n a r e r u t a r e p m e t e g a r o t st g t s 0 5 1 + o t 5 6 -c . c e s 0 1 ) g n i r e d l o s ( e r u t a r e p m e t d a e lt d a e l 0 0 3c note: (1) specification refers to application circuit in figure 1. unless specified: -0 < j < 125c; v cc = 5v; 4v < v bst < 26v r e t e m a r a pl o b m y ss n o i t i d n o cn i mp y tx a ms t i n u y l p p u s r e w o p e g a t l o v y l p p u sv c c v c c 5 1 . 450 . 6v g n i t a r e p o , t n e r r u c t n e c s e i u qp o _ q iv c c c , v 5 = o v o =1 a m t n e r r u c t n e c s e i u qy b t s _ q iv o = n e0 1a t u o k c o l e g a t l o v r e d n u d l o h s e r h t t r a t sv t r a t s 2 . 44 . 46 . 4v s i s e r e t s y hs y h v o l v u 5 0 . 0v d l o h s e r h t e v i t c a c i g o lv t c a 5 . 1v n e e g a t l o v t u p n i l e v e l h g i hv h i 0 . 2v e g a t l o v t u p n i l e v e l w o lv l i 8 . 0v exceeding the specifications below may result in permanent damage to the device, or device malfunction. operation outside of th e parameters specified in the electrical characteristics section is not implied.
3 ? 2004 semtech corp. www.semtech.com power management sc1205 r e t e m a r a pl o b m y ss n o i t i d n o cn i mp y tx a ms t i n u o c e g a t l o v t u p n i l e v e l h g i hv h i 0 . 2v e g a t l o v t u p n i l e v e l w o lv l i 8 . 0v n w o d t u h s l a m r e h t t n i o p p i r t e r u t a r e p m e t r e v ot p t o 5 6 1c s i s e r e t s y ht t s y h 0 1c r e v i r d e d i s h g i h t n e r r u c t u p t u o k a e pi h k p 3a e c n a t s i s e r t u p t u oc r s r g t k n i s r g t , s 0 0 1 < w p t , % 2 < e l c y c y t u d t j v , c 5 2 1 = t s b v - n r d , v 5 . 4 = v g t v + ) c r s ( v 0 . 4 = n r d v r o g t v + ) k n i s ( v 5 0 . 0 = n r d 1 7 . ? r e v i r d e d i s - w o l t n e r r u c t u p t u o k a e pi l k p 3a e c n a t s i s e r t u p t u oc r s r g b k n i s r g b , s 0 0 1 < w p t , % 2 < e l c y c y t u d t j 5 2 1 = o , c v s v v , v 6 . 4 = g b , ) c r s ( v 4 = v r o r d w o l ) k n i s ( v 5 . 0 = 2 . 1 0 . 1 ? ? electrical characteristics (cont.) ac operating specifications r e t e m a r a pl o b m y ss n o i t i d n o cn i mp y tx a ms t i n u r e v i r d e d i s h g i h e m i t e s i rr t 1 g t v , f n 3 = i c t s b v - n r d , v 6 . 4 = t j c 5 2 1 + 4 1 3 2 s n e m i t l l a ff t g t v , f n 3 = i c t s b v - n r d , v 6 . 4 = t j c 5 2 1 + 2 1 9 1 s n , e m i t y a l e d n o i t a g a p o r p h g i h g n i o g g t h d p t g t v , f n 3 = i c t s b v - n r d , v 6 . 4 = t j c 5 2 1 + 0 2 2 3 s n , e m i t y a l e d n o i t a g a p o r p w o l g n i o g g t l d p t g t v , f n 3 = i c t s b v - n r d , v 6 . 4 = t j c 5 2 1 + 5 1 4 2 s n r e v i r d e d i s - w o l e m i t e s i rr t g b v , f n 3 = i c s v , v 6 . 4 = t j c 5 2 1 + 5 1 4 2 s n note: (1) this device is esd sensitive. use of standard esd handling precautions is required.
4 ? 2004 semtech corp. www.semtech.com power management sc1205 timing diagrams r e t e m a r a pl o b m y ss n o i t i d n o cn i mp y tx a ms t i n u r e v i r d e d i s - w o l e m i t l l a fr t g b v , f n 3 = i c s v , v 6 . 4 = t j c 5 2 1 + 3 1 1 2 s n e m i t y a l e d n o i t a g a p o r p h g i h g n i o g g b h d p t i h g b v , f n 3 = i c s v , v 6 . 4 = t j c 5 2 1 + 2 1 9 1 s n e m i t y a l e d n o i t a g a p o r p w o l g n i o g g b l d p t i h g b v , f n 3 = i c s v , v 6 . 4 = t j c 5 2 1 + 7 2 1 s n t u o k c o l e g a t l o v - r e d n u p u g n i p m a r 5 _ vh d p t o l v u h g i h s i n e0 1s n w o d g n i p m a r 5 _ vl d p t o l v u h g i h s i n e0 1s ac operating specifications (cont.)
5 ? 2004 semtech corp. www.semtech.com power management sc1205 pin configuration ordering information pin descriptions top view (so-8) notes: (1) only available in tape and reel packaging. a reel contains 2500 devices. (2) lead free product. this product is fully weee and rohs compliant. e c i v e d ) 1 ( e g a k c a pt ( e g n a r p m e t j ) r t . s c 5 0 2 1 c s 8 - o sc 5 2 1 o t 0 t r t s c 5 0 2 1 c s ) 2 ( # n i pe m a n n i pn o i t c n u f n i p 1n r d n i p s i h t . s ' t e f s o m s u o n o r h c n y s d n a g n i h c t i w s e h t f o n o i t c n u j e h t o t s t c e n n o c n i p s i h t . n o i t a r e p o g n i t c e f f a t u o h t i w d n g p o t e v i t a l e r m u m i n i m v 2 - a o t d e t c e j b u s e b n a c 2g t . t e f s o m ) e d i s - h g i h ( g n i h c t i w s e h t r o f e v i r d e t a g t u p t u o 3t s b e h t p o l e v e d o t s n i p n r d d n a t s b n e e w t e b d e t c e n n o c s i r o t i c a p a c a . n i p p a r t s t o o b y l l a c i p y t s i e u l a v r o t i c a p a c e h t . t e f s o m e d i s - h g i h e h t r o f e g a t l o v p a r t s t o o b g n i t a o l f . ) c i m a r e c ( f 1 d n a f 1 . 0 n e e w t e b 4o c. s r e v i r d t e f s o m e h t o t l a n g i s t u p n i l e v e l - l t t 5n e g b d n a g t , w o l n e h w . e c i v e d e h t f o y r t i u c r i c l a n r e t n i e h t s e l b a n e n i p s i h t , h g i h n e h w . a 0 1 n a h t s s e l s i ) v 5 ( t n e r r u c y l p p u s e h t d n a w o l d e c r o f e r a 6s v y r e v d n g p o t v 5 m o r f d e t c e n n o c e b d l u o h s r o t i c a p a c c i m a r e c f 1 - 2 2 . a . y l p p u s v 5 + . n i p s i h t o t e s o l c 7g b. t e f s o m ) m o t t o b ( s u o n o r h c n y s e h t r o f e v i r d t u p t u o 8d n g p. d n u o r g note: (1) all logic level inputs and outputs are open collector ttl compatible.
6 ? 2004 semtech corp. www.semtech.com power management sc1205 block diagram applications information sc1205 is a high speed, smart dual mosfet driver. it is designed to drive low rds_on power mosfet?s with ultra-low rise/fall times and propagation delays. as the switching frequencies of pwm controllers is increased to reduce power supply volume and cost, fast rise and fall times are necessary to minimize switching losses (top mosfet) and reduce dead-time (bottom mosfet). while low rds_on mosfet?s present a power saving in i 2 r losses, the mosfet?s die area is larger and thus the effective input gate capacitance of the mosfet is in- creased. often a 50% decrease in rds_on more than doubles the effective input gate charge, which must be supplied by the driver. the rds_on power savings can be offset by the switching and dead-time losses with a sub_optimum driver. while discrete solutions can achieve reasonable drive capability, implementing shoot-through and other housekeeping functions necessary for safe operation can become cumbersome and costly. the sc120x family of parts presents a total solution for the high-speed high power density applications. wide input supply range of 4.5v-25v allows use in battery powered applications, new high voltage, distributed power serv- ers as well as class-d amplifiers. theory of operation the control input (co) to the sc1205 is typically supplied by a pwm controller that regulates the power supply out- put. (see application evaluation schematic, figure 4). the timing diagram demonstrates the sequence of events by which the top and bottom drive signals are applied. the shoot-through protection is implemented by holding the bottom fet off until the voltage at the phase node (intersection of top fet source, the output inductor and the bottom fet drain) has dropped below 1v. this as- sures that the top fet has turned off and that a direct current path does not exist between the input supply and ground. the top fet gate drive is turned on after the bottom gate drive has gone low and an internal delay time of 20ns has expired. layout guidelines as with any high speed , high current circuit, proper lay- out is critical in achieving optimum performance of the sc1205. the evaluation board schematic (refer to fig- ure 3) shows a two-phase synchronous design with all surface mountable components. while components connecting to en are relatively non- critical, tight placement and short, wide traces must be used in layout of the gate drives, drn, and especially pgnd pin. the top gate driver supply voltage is provided by bootstrapping the +5v supply and adding it to the phase node (drn) voltage . since the bootstrap capaci- tor supplies the charge to the top gate, it must be less than .5? away from the sc1205. ceramic x7r capaci- tors are a good choice for supply bypassing near the chip. the vcc pin capacitor must also be less than .5? away from the sc1205. the ground node of this capacitor,
7 ? 2004 semtech corp. www.semtech.com power management sc1205 the sc1205 pgnd pin and the source of the bottom fet must be very close to each other, preferably with common pcb copper land with multiple vias to the ground plane (if used). the parallel schottky (if used) must be physically next to the bottom fet?s drain and source pins. any trace or lead inductance in these connections will drive current way from the schottky and allow it to flow through the fet?s body diode, thus reducing efficiency. preventing inadvertent bottom fet turn-on at high input voltages, (12v and greater) a fast turn-on of the top fet creates a positive going spike on the bot- tom fet?s gate through the miller capacitance, crss of the bottom fet. the voltage appearing on the gate due to this spike is: where ciss is the input gate capacitance of the bottom fet. this is assuming that the impedance of the drive path is too high compared to the instantaneous imped- ance of the capacitors. (since dv/dt and thus the effec- tive frequency is very high). if the bg pin of the sc1205 is very close to the bottom fet, vspike will be reduced depending on trace inductance, rate of rise of current, etc. while not shown in figure 4, a capacitor may be added from the gate of the bottom fet to its source, preferably less than .5? away. this capacitor will be added to ciss in the above equation to reduce the effective spike volt- age. the bottom mosfet must be selected with attention paid to the crss/ciss ratio. a low ratio reduces the miller feedback and thus reduces vspike. also mosfets with higher turn-on threshold voltages will conduct at a higher voltage and will not turn on during the spike. the mosfet shown in the schematic (figure 4) has a 2 volt threshold and will require approximately 4.5 volts vgs to be con- ducting, thus reducing the possibility of shoot-through. a zero ohm bottom fet gate resistor will obviously help keeping the gate voltage low during off time. ultimately, slowing down the top fet by adding gate re- sistance will reduce di/dt which will in turn make the ef- fective impedance of the capacitors higher, thus allow- ing the bg driver to hold the bottom gate voltage low. it applications information (cont.) does this at the expense of increased switching times (and switching losses) for the top fet. ringing on the phase node the top mosfet source must be close to the bottom mosfet drain to prevent ringing and the possibility of the phase node going negative. this frequency is deter- mined by: where: l st = the effective stray inductance of the top fet added to trace inductance of the connection between top fet?s source and the bottom fet?s drain added to the trace resistance of the bottom fet?s ground connection. coss=drain to source capacitance of bottom fet. if there is a schottky used, the capacitance of the schottky is added to this value. although this ringing does not pose any power losses due to a fairly high q, it could cause the phase node to go too far negative, thus causing improper operation, double pulsing or at worst driver damage. on the sc1205, the drain node, drn, can go as far as 2v below ground with- out affecting operation or sustaining damage. the ringing is also an emi nuisance due to its high reso- nant frequency. adding a capacitor, typically 1000- 2000pf, in parallel with coss of the bottom fet can of- ten eliminate the emi issue. if double pulsing, due to excessive ringing, placing a 4.7-10 ohm resistor between the phase node and the drn pin of the sc1205 should eliminate the double pulsing. the negative voltage spikes on the phase node adds to the bootstrap capacitor voltage, thus increasing the volt- age between vbst - vdrn. if the phase node negative spikes are too large, the voltage on the boost capacitor could exceed device?s absolute maximum rating of 7v. to eliminate the effect of the ringing on the boost ca- pacitor voltage, place a 4.7 - 10 ohm resistor between boost schottky diode and vcc to filter the negative spikes on drn pin. alternately, a silicon diode, such as the commonly available 1n4148 can substitute for the schottky diode and eliminate the need for the series re- sistor. ciss crss ( crss * vin v spike + = ) coss * l ( sqrt * 2 ( 1 fring st =
8 ? 2004 semtech corp. www.semtech.com power management sc1205 proper layout will guarantee minimum ringing and elimi- nate the need for external components. use of so-8 or other surface mount mosfets while increasing thermal resistance, will reduce lead inductance as well as radi- ated emi. applications information (cont.) over temp shutdown the sc1205 will shutdown by pulling both driver if its junction temperature, t j , exceeds 165 c. typical performance plots figure 1: pwm input and gate drive switch- ing waveforms. the mosfets driven are fdb7030bl . see figure 4 (evaluation board schematic) ch1: pwm input signal ch2: top gate drive ch3: phase (switching) node ch4: bottom gate figure 2: pwm input and gate drive and phase node switching waveforms with time scale expanded. the mosfets driven are fdb7030bl . see figure 4 (evaluation board schematic) ch1: pwm input signal ch2: top gate drive ch3: phase (switching) node ch4: bottom gate
9 ? 2004 semtech corp. www.semtech.com power management sc1205 typical performance plots figure 3: pwm input and gate drive and phase node switching waveforms with time scale expanded. the mosfets driven are fdb7030bl . see figure 4 (evaluation board schematic) ch1: pwm input signal ch2: top gate drive ch3: phase (switching) node ch4: bottom gate
10 ? 2004 semtech corp. www.semtech.com power management sc1205 evaluation board schematic - 3sc1205 figure 4- microprocessor core supply en vc ore vin local gnd +5v en +5v en vin 1.7v ttib1106-708 l2 r5 0 r9 0 r13 0 c22 .1 c15 .1 10u,cer c31 10u,cer c29 10u,cer c24 10u,cer c23 10u,cer c20 10u,cer c19 10u,cer c17 10u,cer c28 10u,cer c16 r11 10k c25 10 0 p f r10 100k r2 10 r14 11.5k fdb7030bl q1 j1 input 1 2 3 4 5 6 1u,16v c9 1uf c1 1uf c4 10u,cer c2 10u,cer c3 1uf c26 r17 6.49k 10u,cer c6 s1 vout /clk sw it ch 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 r18 1 820uf,16v c12 820uf,16v c7 d7 ll42 r19 26.7k r20 10k fdb7030bl q4 ttib1106-708 l1 820uf,16v c14 r8 0 820uf,os c33 820uf,16v c5 820uf,16v c35 820uf,16v c10 820uf,16v c34 r30 133 r31 100 r33 10 . 0k 22nf c11 u2 sc2422a 12 9 2 3 1 13 7 5 6 11 14 4 10 15 16 8 out2 gnd vid3 vid2 vid4 out1 fb vid0 errout oc- oc+ vid1 uvlo bg o ut vcc rref c18 1uf r32 24 . 3k r3 10 .1 c21 r1 .005 r99 0 ^ 4.7-10 ohm u3 sc1205s 4 3 2 1 6 5 7 8 co bst tg drn vs en bg gnd d6 ll42 ^ 4.7-10 ohm 1uf c13 u1 sc1205s 4 3 2 1 6 5 7 8 co bst tg drn vs en bg gnd fdb7030bl q5 fdb7030bl q3 enable cut at x and install r99 to enable driver side uvlo * * * x ^ install resistor to limit voltage rise on boost capacitor due to large phase node negative spikes.
11 ? 2004 semtech corp. www.semtech.com power management sc1205 evaluation board bill of materials m e t iy t qe c n e r e f e r e u l a v / r e b m u n t r a pr e r u t c a f u n a m 15 6 2 c , 8 1 c , 3 1 c , 4 c , 1 cf u 1 22 1, 0 2 c , 9 1 c , 7 1 c , 6 1 c , 6 c , 3 c , 2 c 1 3 c , 9 2 c , 8 2 c , 4 2 c , 3 2 c r e c , u 0 1 37 5 3 c , 4 3 c , 4 1 c , 2 1 c , 0 1 c , 7 c , 5 c v 6 1 , f u 0 2 8c i n o s a n a p 41 9 cv 6 1 , u 1 51 1 1 cf n 2 2 63 2 2 c , 1 2 c , 5 1 c1 . 71 5 2 cf p 0 0 1 81 3 3 c s o , f u 0 2 8o y n a s 92 6 d , 7 d2 4 l l 0 11 1 j 1 12 1 l , 2 l , 8 0 7 - 6 0 1 1 b i t t h n 0 0 7 o c l a f 2 14 5 q , 4 q , 3 q , 1 q l b 0 3 0 7 b d fd l i h c r i a f 3 11 1 r5 0 0 .e l a d 4 12 3 r , 2 r0 1 5 15 9 9 r , 3 1 r , 9 r , 8 r , 5 r0 6 11 0 1 rk 0 0 1 7 12 0 2 r , 1 1 rk 0 1 8 11 4 1 rk 5 . 1 1 9 11 7 1 rk 9 4 . 6 0 21 8 1 r1 1 21 9 1 rk 7 . 6 2 2 21 0 3 r3 3 1 3 21 1 3 r0 0 1 4 21 2 3 rk 3 . 4 2 5 21 3 3 rk 0 . 0 1 6 21 1 s 7 22 1 u , 3 u5 0 2 1 c sh c e t m e s 8 21 2 u a 2 2 4 2 c sh c e t m e s 9 21 l a n o i t p o m h o 0 1 - 7 . 4
12 ? 2004 semtech corp. www.semtech.com power management sc1205 outline drawing - so-8 land pattern - so-8 (.205) (5.20) z g y p (c) 3.00 .118 1.27 .050 0.60 .024 2.20 .087 7.40 .291 x inches dimensions z p y x dim c g millimeters this land pattern is for reference purposes only. consult your manufacturing group to ensure your company's manufacturing guidelines are met. notes: 1. reference ipc-sm-782a, rlp no. 300a. 2. see detail detail a a .050 bsc .236 bsc 8 .010 .150 .189 .154 .193 .012 - 8 0.25 1.27 bsc 6.00 bsc 3.90 4.90 - .157 .197 3.80 4.80 .020 0.31 4.00 5.00 0.51 bxn 2x n/2 tips seating aaa c e/2 2x 12 n a d a1 e1 bbb c a-b d ccc c e/2 a2 (.041) .004 .008 - .028 - - - - 0 .016 .007 .049 .004 .053 8 0 0.20 0.10 - 8 0.40 0.17 1.25 0.10 .041 .010 .069 .065 .010 1.35 (1.04) 0.72 - 1.04 0.25 - - - 1.75 1.65 0.25 0.25 - .010 .020 0.50 - c l (l1) 01 0.25 gage plane h h 3. dimensions "e1" and "d" do not include mold flash, protrusions or gate burrs. -b- controlling dimensions are in millimeters (angles in degrees). datums and to be determined at datum plane notes: 1. 2. -a- -h- side view a b c d e h plane reference jedec std ms-012, variation aa. 4. l1 n 01 bbb aaa ccc a b a2 a1 d e e1 l h e c dim min millimeters nom dimensions inches min max max nom e h c n a r b n a w i a t 0 8 3 3 - 8 4 7 2 - 2 - 6 8 8 : l e t fx a0 9 3 3 - 8 4 7 2 - 2 - 6 8 8 : h b m g d n a l r e z t i w s h c e t m e s h c n a r b n a p a j 0 5 9 0 - 8 0 4 6 - 3 - 1 8 : l e t 1 5 9 0 - 8 0 4 6 - 3 - 1 8 : x a f h c n a r b a e r o k tl e7 7 3 4 - 7 2 5 - 2 - 2 8 : f6 7 3 4 - 7 2 5 - 2 - 2 8 : x a ) . k . u ( d e t i m i l h c e t m e s 0 0 6 - 7 2 5 - 4 9 7 1 - 4 4 : l e t 1 0 6 - 7 2 5 - 4 9 7 1 - 4 4 : x a f e c i f f o i a h g n a h s t0 3 8 0 - 1 9 3 6 - 1 2 - 6 8 : l e 1 3 8 0 - 1 9 3 6 - 1 2 - 6 8 : x a f l r a s e c n a r f h c e t m e s 0 0 - 2 2 - 8 2 - 9 6 1 ) 0 ( - 3 3 : l e t 8 9 - 2 1 - 8 2 - 9 6 1 ) 0 ( - 3 3 : x a f f o y r a i d i s b u s d e n w o - y l l o h w a s i g a l a n o i t a n r e t n i h c e t m e s . a . s . u e h t n i s r e t r a u q d a e h s t i s a h h c i h w , n o i t a r o p r o c h c e t m e s h b m g y n a m r e g h c e t m e s 3 2 1 - 0 4 1 - 1 6 1 8 ) 0 ( - 9 4 : l e t 4 2 1 - 0 4 1 - 1 6 1 8 ) 0 ( - 9 4 : x a f contact information for semtech international ag

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